Tuesday 12 April 2016

LAYOUT AND PHYSICAL DESIGN ENGINEER

JOB DESCRIPTION:

Include all aspects of physical design including synthesis, floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM and Tape Out.
 
Should be able to interface with Front End Design team to resolve Design Issues

REQUIRED SKILLS:
  • Must possess 3-7 years of hands on experience, P&R from RTL to GDS including timing closure and Physical verification. 
  • Design experience in all aspects of physical design. 
  • Proficient and powerful user of Synopsys Tool Suite (DC/ICC/Star/PT). 
  • Technologies: 28nm and below.
  • Experience in Mentor Calibre tools to run Physical verification 
  • Experience in Cadence Voltus to run IR-analysis is a Plus. 
  • Experience in Tcl/Tk, PERL, Makefile is a Plus 
  • Excellent verbal and written communication skill is required. 
  • Excellent interpersonal and analytical skills with an ability to work independently and within a team is required.
  • Highly motivated, excellent team player, and customer oriented.
If job seems relevant, kindly send your profile to jobs@toss-ex.com

TEST ENGINEER

JOB DESCRIPTION:

Looking for Test engineer with proficiency in VHDL/verilog coding, test bench setup, test case creation and verificaion.

SKILLS REQUIRED:
  • Experience in Design for Test (DFT) of large, lower geometry SOC designs.
  • Experience in DFT concepts, test mode.
  • Good knowledge in Boundary Scan, ATPG Scan, and memory testing.
  • Proficiency in VHDL/Verilog coding, test bench setup, test case creation and verification
  • Proficiency in mixed signal IP verification such PCIe Phy, PLL etc
  • Experience with industry standard tools for DFT and Verification (Synopsys, Cadence)
  • Proficiency high level programming and scripting languages such as “C”, “C++”, Perl
  • Knowledge or Experience in Test development and Product engineering will be an added advantages
  • if u find this opening relevant,kindly send your resume to jobs@toss-ex.com

FUNCTIONAL VERIFICATION ENGINEER

JOB DESCRIPTION:

Looking for an experienced HVL(Hardware verification Language) like specman( e ) and creating verification environments , eVC’s and test cases using ‘e’ on industry standard simulators.

DESIRED SKILLS:
  • Masters or Bachelor’s degree in Electrical Engineering, Communications or an equivalent university program.
  • 5+ years of experience in pre-silicon Verification based on digital designs.
  • Prior Experience in verifying Packet Processors , buffer managers ,DMA, QoS specific blocks is also an added advantage.
  • Domain Knowledge of Ethernet L2/L3 Switching concepts and deep understanding of Ethernet protocols.
  • Candidate should have a deeper understanding of various verification signoff processes like coverage driven methodologies , constraint random verification and can develop complete test plans based on the same.
  • Excellent design debug  and root causing capabilities would be preferred.
  • Knowledge of UNIX/Linux based scripting Languages like perl , python.
  • In Depth understanding of VLSI verification flows also using in-circuit hardware emulators is an added advantage.
  • Good Communication skills , Open and Collaborative working style within large international teams.

If the position seems relevant, send your profile to jobs@toss-ex.com

DIGITAL DESIGN ENGINEER

JOB DESCRIPTION:

                    Looking for digital design engineer with excellent designing skills and having a good understanding of timing   closure and reated methodologies like synthesis and STA using synopys toolset.

SKILLS REQUIRED:
  • Masters or Bachelor’s degree in Electrical Engineering, Communications or an equivalent university program.
  • 5+ years of experience in RTL based digital design (VHDL/Verilog)
  • In Depth knowledge on Digital Signal Processing sub-blocks like Digital filters, FFT , IFFT , Digital Echo Cancellers would be mandatory.
  • Domain Knowledge on Ethernet physical layer is an added advantage.
  • Candidate having experience in SoC , Module integration would also be an added advantage.
  • Candidate should have a good understanding of various verification methodologies and should be able to signoff his block with sanity simulations using VHDL/Verilog.
  • Knowledge of UNIX/Linux based scripting Languages like perl , python.
  • In Depth understanding of VLSI Design flows also involving DfT is an added advantage.
  • Good Communication skills , Open and Collaborative working style within large international teams.


Kindly send the updated profile if job seems relevant.

e-mail:jobs@toss-ex.com